Data representation and arithmetic explain how a computer stores numbers and performs operations, while bus organization and instruction cycle explain how data and control move inside the machine. PSC Computer Engineer questions can be numerical, conceptual and diagram-based, so this note focuses on conversion, complements, overflow, ALU logic, bus signals and fetch-decode-execute flow.

Concept Teaching

A processor does not understand decimal numbers directly; it manipulates bit patterns. The same 8 bits can mean unsigned number, signed number, character or instruction depending on interpretation. Arithmetic circuits operate on these bit patterns, buses move them between units, and the instruction cycle coordinates when each transfer and operation happens.

Number Systems and Positional Weight

Binary, octal, decimal and hexadecimal are positional systems. The base decides digit set and place value.

• Binary base 2 uses digits 0 and 1.
• Octal base 8 uses digits 0 to 7 and maps neatly to 3 binary bits.
• Decimal base 10 uses digits 0 to 9.
• Hexadecimal base 16 uses digits 0 to 9 and A to F and maps neatly to 4 binary bits.
• Hex is widely used for memory addresses, machine code and bit masks because it is compact.
• Conversion skill is essential for MCQ and short numerical questions.

Binary, Octal and Hex Conversion

Use grouping methods to avoid slow decimal conversion when converting between binary, octal and hexadecimal.

• Binary to octal: group bits in sets of 3 from right side for integer part.
• Binary to hex: group bits in sets of 4 from right side for integer part.
• Octal to binary: replace each octal digit by 3-bit binary equivalent.
• Hex to binary: replace each hex digit by 4-bit binary equivalent.
• For fractional bits, group from left side after binary point.
• Exam trap: add leading zeros only for grouping; they do not change value.

Unsigned and Signed Integers

The same bit pattern has different value depending on representation.

Two’s Complement Arithmetic

Two’s complement is important because subtraction can be performed using addition hardware.

• To represent -X in n bits: write X in binary, invert all bits, add 1.
• Subtraction A – B can be done as A + two’s complement of B.
• Ignore carry out from the MSB in fixed-width two’s complement arithmetic.
• Sign extension preserves value when increasing bit width.
• For positive numbers, extend with 0; for negative numbers, extend with 1.
• Exam trap: carry out and overflow are different concepts.

Overflow Detection

Overflow means the mathematical result does not fit in available signed/unsigned range.

• Unsigned addition overflow is indicated by carry out from MSB.
• Signed two’s complement overflow occurs when adding two same-sign numbers gives opposite-sign result.
• Positive + positive should not become negative.
• Negative + negative should not become positive.
• Adding opposite signs cannot overflow in two’s complement addition.
• Overflow flag is used by CPU status register/condition codes.

Fixed-Point and Floating-Point Idea

PSC questions may ask representation concept even without deep IEEE-754 calculation.

• Fixed-point keeps binary point at fixed position; simple and fast but limited range.
• Floating-point represents number using sign, exponent and mantissa/significand.
• Floating-point supports very large and very small numbers but may have rounding error.
• Scientific notation idea: value is scaled by base raised to exponent.
• IEEE-style floating point uses normalized representation for precision.
• Exam trap: floating point is approximate for many decimal fractions.

Character and Instruction Representation

Not all bit patterns are numbers. Architecture interprets bits based on context.

• ASCII uses 7-bit character encoding; extended variants use 8 bits.
• Unicode represents characters from many languages using code points and encodings such as UTF-8.
• Instruction word contains fields such as opcode, register specifier, address/immediate value and mode bits.
• Opcode tells the CPU what operation to perform.
• Operand fields identify registers, memory addresses or immediate constants.
• Instruction format affects decoding complexity and code density.

ALU and Arithmetic Operations

ALU performs arithmetic and logic operations using combinational circuits controlled by operation-select lines.

• Adder is the core building block for addition and subtraction.
• Half adder adds two bits; full adder adds two bits plus carry-in.
• Ripple-carry adder is simple but carry propagation delay grows with bit width.
• Carry lookahead adder improves speed by computing carry signals earlier.
• Logic operations include AND, OR, XOR, NOT and shifts.
• Status flags commonly include zero, carry, sign/negative and overflow.

Bus Organization

Buses connect CPU, memory and I/O. A bus is more than data wires; it includes address and control meaning.

Bus Width, Bandwidth and Arbitration

Bus performance depends on width, clocking, protocol and contention.

• Address bus width determines maximum addressable locations.
• Data bus width determines how many bits can transfer per bus cycle.
• Bus bandwidth depends on width and transfer rate.
• Shared bus allows only one master to drive bus at a time.
• Bus arbitration decides which device gets bus control.
• DMA controller may become bus master to transfer data without continuous CPU involvement.

Instruction Cycle in Detail

Instruction cycle is a sequence of register transfers and control signals.

• Fetch: MAR gets address from PC; memory read occurs; instruction goes to MDR/IR; PC increments.
• Decode: control unit interprets opcode and addressing mode.
• Effective address calculation may be needed for memory operands.
• Operand fetch reads register or memory data.
• Execute performs ALU, branch, memory or I/O action.
• Writeback stores result into destination register or memory.
• Interrupt check may occur after instruction completion.

Engineering Mechanism

• A program stores instructions and data as binary patterns in memory.
• CPU fetches instruction using program counter and address bus.
• Instruction bits enter instruction register and are decoded by control unit.
• Operands are fetched from registers or memory through internal/system buses.
• ALU performs arithmetic/logic operation and sets status flags.
• Result is written back to register or memory.
• Program counter is updated for next sequential instruction or changed by branch/interrupt.

Diagrams / Models To Draw

• Draw bit grouping for binary to octal and hexadecimal conversion.
• Draw signed number line for 4-bit two’s complement range.
• Draw full adder and ripple-carry adder concept.
• Draw ALU block with operation select lines and status flags.
• Draw system bus with address bus, data bus and control bus.
• Draw instruction cycle flow: fetch, decode, operand fetch, execute, writeback, interrupt check.

Formulas, Tables and Algorithms

• Unsigned n-bit range = 0 to 2^n – 1.
• Two’s complement n-bit range = -2^(n-1) to 2^(n-1) – 1.
• Number of addressable locations = 2^(address bus width).
• Approximate bus bandwidth = bus width in bits x transfer rate.
• Two’s complement of X = bitwise complement of X + 1.
• CPU status flags commonly include ZF, CF, SF/NF and OF.

Worked Example

Represent -5 in 8-bit two’s complement. First write +5 = 00000101. Invert bits: 11111010. Add 1: 11111011. So -5 is 11111011. If we add +5 and -5: 00000101 + 11111011 = 1 00000000; in 8-bit result is 00000000 and carry out is ignored, giving zero.

Subjective Answer Pattern

• Define data representation and explain why binary is used.
• Explain number systems and conversion grouping.
• Compare unsigned, sign-magnitude, one’s complement and two’s complement.
• Explain arithmetic operations, overflow and ALU flags.
• Explain bus organization: address, data and control buses.
• Describe instruction cycle with register-transfer style steps.
• Conclude by linking representation, buses and instruction execution.

Common Engineering Mistakes

• Solving signed arithmetic without saying whether it is sign-magnitude, one’s complement or two’s complement.
• Confusing carry flag with overflow flag.
• Forgetting that hexadecimal digit equals 4 binary bits.
• Saying address bus carries data values.
• Leaving out PC, IR or MAR/MDR in instruction cycle answer.
• Thinking floating-point represents all decimal values exactly.
• Ignoring sign extension when increasing signed integer bit width.

MCQ Revision

• What is the unsigned range of 8 bits?
• What is the two’s complement range of n bits?
• How is two’s complement of a number obtained?
• When does signed overflow occur in addition?
• Which bus selects memory location?
• Which CPU register holds current instruction?
• Which register stores address of next instruction?
• What does ALU overflow flag indicate?

Final Summary

• Computers store numbers, characters and instructions as binary patterns.
• Two’s complement is the dominant signed integer representation.
• Overflow depends on bit width and representation.
• ALU performs arithmetic/logic and updates status flags.
• Address, data and control buses move information among CPU, memory and I/O.
• Instruction cycle coordinates fetch, decode, execute and writeback operations.