Counters, registers and IC families extend flip-flop theory into practical digital systems. PSC questions often test counter modulus, shift-register operation, synchronous versus ripple counters, timing hazards and TTL/CMOS family characteristics.
Engineering Definitions
Counter
Standard definition: A sequential circuit that moves through a prescribed sequence of states on clock pulses.
Exam meaning: Clock pulse अनुसार count/state change गर्ने sequential circuit।
Register
Standard definition: A group of flip-flops used to store a multi-bit binary value.
Exam meaning: Multiple bits store गर्ने flip-flop collection।
Shift register
Standard definition: A register that shifts stored bits left or right on clock pulses.
Exam meaning: Data bits लाई serial/parallel रूपमा shift गर्ने register।
Modulus
Standard definition: The number of distinct states through which a counter cycles before repeating.
Exam meaning: Counter repeat हुनु अघि जाने total states।
IC family
Standard definition: A group of logic integrated circuits built using similar circuit technology and electrical characteristics.
Exam meaning: TTL, CMOS जस्ता same technology logic chips को family।
Concept Teaching
Counters and registers are built from flip-flops, but their behavior is determined by connection and clocking. Ripple counters are simple but slow due to propagation delay. Synchronous counters are faster because all flip-flops share the same clock. IC families matter because voltage, speed, power, fan-out and noise margin decide whether a circuit works reliably.
Registers and Shift Registers
Registers store multi-bit data; shift registers also move data bit by bit.
- Parallel-in parallel-out register loads and reads all bits together.
- Serial-in serial-out register shifts one bit per clock.
- Serial-in parallel-out converts serial data to parallel.
- Parallel-in serial-out converts parallel data to serial.
- Bidirectional shift register can shift left or right.
- Universal shift register supports hold, shift left, shift right and parallel load.
Counters
Counters are used for counting events, frequency division, timing and sequence generation.
| Counter type | Working idea | Exam point |
|---|---|---|
| Ripple/asynchronous | Flip-flop output clocks next stage | Simple but cumulative delay |
| Synchronous | All flip-flops share same clock | Faster and easier to control |
| Up counter | Counts increasing sequence | Binary count upward |
| Down counter | Counts decreasing sequence | Binary count downward |
| Ring counter | One active bit circulates | Needs n flip-flops for n states |
| Johnson counter | Inverted last output fed back | n flip-flops produce 2n states |
Counter Design Concepts
Design questions need modulus, state sequence and flip-flop input equations.
- Number of flip-flops needed for MOD-N counter is ceil(log2 N).
- Unused states must be handled or forced back to valid sequence.
- Synchronous counter design uses present-state/next-state table.
- Ripple counter propagation delay limits maximum operating frequency.
- Frequency division: a binary flip-flop divides clock frequency by 2.
- A cascade of n toggle flip-flops divides frequency by 2^n.
Timing, Race and Hazard
Sequential circuits fail when timing assumptions break.
- Propagation delay is time between input/clock change and output response.
- Clock skew is difference in clock arrival time at different flip-flops.
- Setup and hold time must be satisfied for reliable storage.
- Race-around can occur in level-triggered JK flip-flop when J=K=1 and clock pulse is too wide.
- Master-slave or edge-triggered flip-flops avoid race-around.
- Glitches can occur due to unequal path delays.
Digital IC Families
IC family comparison is common in MCQ and short notes.
| Family | Strength | Limitation |
|---|---|---|
| TTL | Good speed, robust logic levels | Higher power than CMOS |
| CMOS | Very low static power, high noise immunity | Can be slower in older forms; ESD sensitive |
| ECL | Very high speed | High power consumption |
| Schottky TTL | Faster TTL variant | More power than low-power families |
| BiCMOS | Combines CMOS density and bipolar drive | More complex fabrication |
Engineering Mechanism
- Flip-flops store state bits.
- Combinational logic determines next state or shift path.
- Clock edge updates all synchronous storage elements.
- Counter state advances according to designed sequence.
- Register control signals select hold, load, shift or clear operation.
- IC family electrical parameters determine compatibility and reliable operation.
Diagrams / Models To Draw
- Draw 4-bit register using D flip-flops.
- Draw serial-in serial-out shift register.
- Draw ripple counter and synchronous counter timing difference.
- Draw ring and Johnson counter feedback.
- Draw TTL/CMOS comparison table with power, speed and noise margin.
Formulas, Tables and Algorithms
- Flip-flops required for MOD-N counter = ceil(log2 N).
- n-bit binary counter has 2^n states.
- Ring counter with n flip-flops has n states.
- Johnson counter with n flip-flops has 2n states.
- Ripple counter worst-case delay is approximately n x flip-flop propagation delay.
- Fan-out = number of similar gate inputs driven reliably by one output.
| Concept | Role | Exam distinction |
|---|---|---|
| Register | Stores multi-bit data | Parallel storage |
| Shift register | Moves data serially/parallelly | Conversion and delay line |
| Ripple counter | Simple count sequence | Delay accumulates |
| Synchronous counter | Fast controlled sequence | All flip-flops clock together |
| TTL | Bipolar logic family | Speed/power tradeoff |
| CMOS | MOS logic family | Low power and high noise immunity |
Exam Point
- Always specify counter modulus and number of flip-flops.
- Differentiate ripple and synchronous counters by clocking method.
- For shift registers, mention data input/output mode.
- IC family comparison should include speed, power, fan-out and noise margin.
- Race-around is associated with level-triggered JK behavior.
Worked Example
A MOD-10 counter needs ceil(log2 10) = 4 flip-flops because 3 flip-flops provide only 8 states. Since 4 flip-flops provide 16 states, six unused states must be reset or handled so the sequence returns to 0000 after 1001.
Subjective Answer Pattern
- Define sequential building blocks.
- Explain registers and shift-register modes.
- Compare counter types and design requirements.
- Discuss timing problems and race-around.
- Compare IC families using electrical characteristics.
- Add one modulus or frequency-division example.
Common Engineering Mistakes
- Using floor instead of ceil for counter flip-flop count.
- Saying ring counter has 2^n states.
- Ignoring unused states in MOD-N design.
- Confusing fan-in and fan-out.
- Treating CMOS and TTL as identical voltage/power families.
MCQ Revision
- How many flip-flops are needed for MOD-13 counter?
- Which counter has cumulative propagation delay?
- How many states in n-bit Johnson counter?
- Which IC family has low static power?
- What is fan-out?
- Which shift register converts serial data to parallel?
Final Summary
- Registers store multi-bit values; shift registers move data.
- Counters generate state/count sequences and frequency division.
- Synchronous counters are faster than ripple counters.
- Timing constraints and race conditions affect reliability.
- IC families differ in speed, power, fan-out and noise margin.