Addressing modes, I/O, interrupts, DMA and memory systems explain how a CPU finds operands, communicates with devices and manages fast versus large storage. PSC Computer Engineer questions commonly test effective address calculation, interrupt sequence, DMA advantage, cache mapping and memory hierarchy.

Concept Teaching

A program instruction rarely contains all data directly. It often contains a register name, memory address, displacement or pointer. Addressing modes interpret those fields. Once operands are found, the CPU must also communicate with I/O devices and memory. Interrupts and DMA reduce CPU waiting, while cache and memory hierarchy reduce the speed gap between CPU and main memory.

Why Addressing Modes Matter

Addressing modes make instructions flexible and compact. They allow constants, registers, arrays, pointers, stack frames and relative branches to be represented efficiently.

• Immediate addressing is good for constants.
• Register addressing is fast because operand is inside CPU.
• Direct addressing is simple but address field size limits reachable memory.
• Indirect addressing supports pointers and dynamic data structures.
• Indexed/base-displacement addressing supports arrays and records.
• Relative addressing supports relocatable branch instructions.

Common Addressing Modes

PSC often asks definitions and examples. Always show where the operand is and how effective address is obtained.

Effective Address Examples

For numerical questions, write the formula first, then substitute values.

• Indexed: if base address = 1000 and index register = 20, effective address = 1020.
• Base displacement: if base register = 5000 and displacement = 16, effective address = 5016.
• Relative branch: if PC = 200 and displacement = -12, target effective address = 188.
• Indirect: if address field = 300 and memory[300] = 900, operand is at memory[900].
• Immediate mode does not calculate memory effective address for operand fetch.
• Exam trap: direct address gives operand location; immediate gives operand value.

I/O Organization

I/O connects CPU with devices that are much slower and more diverse than memory.

• I/O interface/controller hides device-specific details from CPU.
• Data register holds data transferred to/from device.
• Status register indicates ready, busy, error or completion state.
• Control register stores command bits such as start, reset or mode.
• Memory-mapped I/O uses normal memory address space for device registers.
• Isolated/port-mapped I/O uses separate I/O address space and special instructions.

Programmed I/O, Interrupt I/O and DMA

These three techniques differ mainly in CPU involvement.

Interrupt Handling Sequence

Interrupt questions need a clean sequence. Think: detect, save, service, restore.

• CPU completes current instruction or reaches interrupt-check point.
• CPU checks interrupt request and priority/mask status.
• Current context such as PC and status register is saved.
• CPU obtains ISR address from interrupt vector table or fixed vector.
• Interrupt service routine executes device/event-specific handling.
• ISR clears interrupt condition or acknowledges device.
• Return-from-interrupt restores context and resumes previous program.

Interrupt Types and Priority

Interrupt systems must handle multiple events safely.

• Hardware interrupt comes from external device.
• Software interrupt/trap is caused by instruction or system call.
• Exception is caused by current instruction, such as divide-by-zero or page fault.
• Maskable interrupt can be disabled; non-maskable interrupt is reserved for critical events.
• Vectored interrupt directly identifies ISR address; non-vectored requires polling/lookup.
• Priority resolves which interrupt is served first.

DMA Operation

DMA improves I/O performance by transferring blocks without CPU moving each unit of data.

• CPU initializes DMA controller with memory address, device, transfer direction and count.
• DMA controller requests bus control.
• Data moves between I/O device and memory directly.
• CPU may be suspended briefly during bus use or share cycles with DMA.
• DMA interrupts CPU after block transfer completion or error.
• DMA is useful for disk, network, audio/video and other high-throughput transfers.
• Exam trap: DMA does not mean CPU is totally absent; CPU sets up and handles completion.

Memory Hierarchy

Memory hierarchy is built because no single storage technology is simultaneously fastest, largest and cheapest.

Cache Memory Basics

Cache exploits locality to keep recently/frequently used data near CPU.

• Temporal locality: recently used data/instruction is likely to be used again.
• Spatial locality: nearby addresses are likely to be used soon.
• Cache hit means requested block is found in cache.
• Cache miss means block must be fetched from lower memory level.
• Cache line/block is the unit transferred between cache and memory.
• Write-through updates cache and memory together; write-back updates memory later when dirty block is evicted.
• Replacement policies decide which cache line to evict, such as LRU/FIFO/random.

Cache Mapping Techniques

Mapping decides where a memory block can be placed in cache.

Virtual Memory Idea

Virtual memory gives each process a logical address space and maps it to physical memory.

• Page is fixed-size block in virtual memory; frame is corresponding block in physical memory.
• Page table maps virtual pages to physical frames.
• MMU translates virtual address to physical address.
• TLB caches recent address translations.
• Page fault occurs when referenced page is not in physical memory.
• Virtual memory improves protection, relocation and ability to run programs larger than RAM.

Engineering Mechanism

• Instruction decoder identifies addressing mode from instruction fields.
• CPU computes effective address using register, displacement, index, PC or memory pointer as required.
• Operand is fetched from register, immediate field or memory.
• For I/O, CPU communicates with device controller registers using memory-mapped or port-mapped access.
• Interrupt lets device request CPU service without continuous polling.
• DMA controller transfers data blocks directly between device and memory after CPU setup.
• Memory hierarchy and cache reduce average memory access time for instruction/data fetches.

Diagrams / Models To Draw

• Draw addressing mode examples: immediate, direct, indirect, indexed and relative.
• Draw I/O controller with data, status and control registers.
• Draw interrupt handling flow: request, save context, vector, ISR, restore.
• Draw DMA transfer path between device controller, memory and bus.
• Draw memory hierarchy pyramid: registers, cache, RAM, SSD/HDD.
• Draw cache mapping: direct, associative and set-associative placement.

Formulas, Tables and Algorithms

• Indexed addressing: EA = base address + index register.
• Base displacement: EA = base register + displacement.
• Relative addressing: EA = PC + displacement.
• Addressable memory locations = 2^(address bits).
• Average memory access time = hit time + miss rate x miss penalty.
• Cache hit ratio = cache hits / total memory accesses.

Worked Example

If an instruction uses base displacement addressing with base register Rb = 4000 and displacement = 120, effective address is 4120. If the operand at memory[4120] is loaded into R1, the CPU first computes EA, sends 4120 on address bus, asserts memory read, receives data on data bus and writes it into R1.

Subjective Answer Pattern

• Define addressing mode and effective address.
• Explain common addressing modes with formulas and examples.
• Explain I/O interface registers and memory-mapped versus isolated I/O.
• Compare programmed I/O, interrupt-driven I/O and DMA.
• Describe interrupt handling sequence.
• Explain memory hierarchy and cache principles.
• Add cache mapping and virtual memory if marks allow.

Common Engineering Mistakes

• Confusing immediate operand with memory address.
• Forgetting PC-relative addressing formula.
• Saying interrupt always occurs between any two machine cycles; usually CPU recognizes at safe instruction boundary/check point.
• Saying DMA needs no CPU at all; CPU initializes and handles completion.
• Mixing cache hit ratio and miss rate.
• Saying address bus transfers data.
• Confusing page fault with general program error.

MCQ Revision

• Which addressing mode has operand inside instruction?
• What is effective address?
• Which I/O method uses busy waiting?
• Which I/O technique transfers blocks with least CPU involvement?
• What does an interrupt vector store?
• What is temporal locality?
• Which cache mapping allows a block anywhere?
• What hardware caches virtual-to-physical address translations?

Final Summary

• Addressing modes specify operand location and effective address calculation.
• I/O uses controller registers and can be programmed, interrupt-driven or DMA-based.
• Interrupt handling saves context, runs ISR and restores execution.
• DMA improves block I/O by reducing CPU transfer overhead.
• Memory hierarchy balances speed, cost and capacity.
• Cache and virtual memory are essential for practical CPU-memory performance.