Sequential circuits are the bridge between digital logic and computer architecture. PSC Computer Engineer questions may ask direct MCQs on latches and flip-flops, short answers on state table/state diagram, and long answers on finite state machine design. This note teaches the concept deeply enough to solve design, trace and comparison questions.

Concept Teaching

Combinational circuits are memoryless: same input always gives same output. Sequential circuits remember. This memory is created using feedback and storage elements such as latches or flip-flops. In architecture, registers, counters, control units, program counters and pipeline stages all depend on sequential circuit principles.

Combinational vs Sequential Logic

The first exam distinction is whether the circuit has memory.

Latches and Flip-Flops

Both store one bit, but timing behavior is different. PSC MCQs often test level-triggered versus edge-triggered behavior.

• Latch is level-sensitive: output can change while enable level is active.
• Flip-flop is edge-triggered: output changes at clock edge, normally rising or falling edge.
• SR latch is basic but has invalid condition when both set and reset are active in certain implementations.
• D flip-flop removes SR ambiguity by using one data input.
• JK flip-flop improves SR behavior: J=K=1 toggles output.
• T flip-flop toggles when T=1 and holds when T=0; useful for counters.

Flip-Flop Characteristic Tables

Characteristic table tells next state from present state and input. Excitation table tells required input to move from present state to desired next state.

Synchronous vs Asynchronous Sequential Circuits

Synchronous circuits change state according to a clock. Asynchronous circuits respond immediately to input changes and feedback delay.

• Synchronous design is easier to analyze and widely used in CPU/register systems.
• Clock coordinates state transitions across flip-flops.
• Asynchronous circuits can be faster in theory but are harder due to races and hazards.
• Race condition occurs when final state depends on order/timing of internal changes.
• Hazard is unwanted temporary output glitch due to unequal propagation delays.
• PSC answer should mention timing, clock, reliability and design complexity.

State Table, State Diagram and State Equation

These are different representations of the same sequential behavior.

• State diagram is best for understanding behavior visually.
• State table is best for systematic design and truth-table conversion.
• State equation gives next-state logic algebraically.
• Output equation gives circuit output from state/input depending on machine type.
• State assignment encodes symbolic states into binary values.
• State minimization removes equivalent states to reduce hardware.

Moore and Mealy Machines

This comparison is extremely important for FSM questions.

FSM Design Procedure

For subjective questions, write the design steps even if the problem is small.

• Understand the required behavior in words.
• Identify inputs, outputs and required memory/state.
• Draw state diagram using symbolic states.
• Prepare state table: present state, input, next state, output.
• Assign binary codes to states.
• Choose flip-flop type: D, JK or T.
• Use excitation/characteristic table to derive flip-flop input equations.
• Minimize Boolean equations using K-map or algebra.
• Draw final logic circuit using gates and flip-flops.
• Verify by tracing input sequence.

Timing Parameters

Sequential design is not only logic equations. Timing determines whether circuit works reliably at a clock frequency.

• Setup time: data must be stable before clock edge.
• Hold time: data must remain stable after clock edge.
• Clock-to-Q delay: time for flip-flop output to change after clock edge.
• Propagation delay: time taken by combinational logic between flip-flops.
• Maximum clock frequency depends on clock period being long enough for flip-flop and combinational delays.
• Setup/hold violation can cause metastability or incorrect state capture.

Architecture Connection

Sequential circuits are not isolated digital-electronics theory; they build real computer architecture blocks.

• Register file stores operands and results using arrays of flip-flops/latches.
• Program counter is a sequential register that holds address of next instruction.
• Instruction register stores current instruction during execution.
• Control unit can be implemented as FSM that generates control signals per state.
• Counters generate address sequences, timing sequences and event counts.
• Pipeline registers separate CPU pipeline stages and store intermediate values.

Engineering Mechanism

• Inputs and present state enter combinational next-state logic.
• Next-state logic computes the value that should be stored at next clock edge.
• Flip-flops capture next state on active clock edge.
• Stored state feeds back into next-state logic.
• Output logic generates output from state only in Moore machine or state plus input in Mealy machine.
• Timing constraints ensure data reaches flip-flop input before setup deadline and remains stable through hold time.

Diagrams / Models To Draw

• Draw general sequential circuit block: input + present state -> combinational logic -> next state -> flip-flops -> present state feedback.
• Draw D flip-flop symbol and timing diagram.
• Draw state diagram with states as circles and transitions as arrows.
• Draw state table with columns: present state, input, next state, output.
• Draw Moore vs Mealy output labeling difference.
• Draw CPU control unit as FSM generating control signals.

Formulas, Tables and Algorithms

• D flip-flop: Q(next) = D.
• T flip-flop: Q(next) = T XOR Q.
• JK flip-flop: Q(next) = JQ bar + K bar Q.
• Number of flip-flops required for N states = ceil(log2 N).
• Clock period must be at least clock-to-Q delay + max combinational delay + setup time + clock skew margin.
• Maximum clock frequency = 1 / minimum safe clock period.

Worked Example

Suppose a sequence detector must output 1 when the last two input bits are 11. Define states S0 = no useful match and S1 = last bit was 1. If input is 1 in S1, output becomes 1. In a Mealy model, output can be placed on transition S1 –1/1–> S1. The state table then lists present state S0/S1, input 0/1, next state and output. One flip-flop is enough because there are two states.

Subjective Answer Pattern

• Define sequential circuit and explain memory/state.
• Compare combinational and sequential logic.
• Explain latch, flip-flop and clocked operation.
• Describe state table, state diagram and state equations.
• Compare Moore and Mealy machines.
• Write FSM design steps and show architecture applications.
• Conclude with timing constraints and reliability points.

Common Engineering Mistakes

• Writing that sequential output depends only on present input.
• Confusing latch and flip-flop timing behavior.
• Forgetting present state column in state table.
• Labeling Moore outputs on transitions instead of states.
• Ignoring setup and hold time in timing questions.
• Using floor(log2 N) instead of ceil(log2 N) for number of flip-flops.
• Treating state diagram as optional in FSM subjective answer.

MCQ Revision

• Sequential circuit output depends on what?
• Which storage element is edge-triggered?
• How many flip-flops are needed for 9 states?
• In Moore machine, output depends on what?
• In Mealy machine, output depends on what?
• What is setup time?
• Which flip-flop toggles when T=1?
• Which table shows present state, input, next state and output?

Final Summary

• Sequential circuits store state; combinational circuits do not.
• Flip-flops, state tables and state diagrams are the core tools for FSM design.
• Moore and Mealy machines differ mainly by output dependency.
• Timing constraints decide whether a sequential circuit works reliably.
• Computer architecture uses sequential circuits in registers, counters, control units and pipelines.