808x microprocessor questions connect computer organization with real low-level programming and hardware interfacing. For PSC Computer Engineer, prepare register organization, flag behavior, addressing modes, instruction types, memory/I/O interfacing, interrupts and bus timing with diagrams and short assembly examples.

Concept Teaching

Microprocessor study should not be memorized as pin lists only. Think in terms of datapath: registers hold operands and addresses, ALU performs operations, flags record result conditions, buses move information, control signals coordinate read/write, and interface circuits decode addresses to select memory or I/O devices.

8085 and 8086 Architecture View

A good exam answer starts with register and bus width differences.

Register Organization and Flags

Registers are high-speed storage inside the processor. Flags are status bits used for conditional branching and arithmetic decisions.

• 8085 has accumulator A, general registers B, C, D, E, H, L, program counter, stack pointer and flag register.
• Register pairs BC, DE and HL are used for 16-bit operations/addressing in 8085.
• 8086 has AX, BX, CX, DX, SP, BP, SI, DI and segment registers CS, DS, SS, ES.
• Important flags include zero, sign, carry, auxiliary carry, parity and overflow in 8086 context.
• Program counter/instruction pointer controls next instruction address.
• Stack pointer tracks top of stack for CALL, RET, PUSH, POP and interrupt handling.

Instruction Types and Addressing

Instruction questions often test what category an instruction belongs to and where operands are found.

• Data transfer instructions move data among register, memory and I/O.
• Arithmetic instructions perform add, subtract, increment, decrement and compare.
• Logical instructions perform AND, OR, XOR, complement, rotate and compare-style operations.
• Branch instructions change control flow conditionally or unconditionally.
• Stack and subroutine instructions support modular program execution.
• Common addressing: immediate, register, direct, register indirect, indexed/base in 8086 style.

8086 Segmentation

Segmentation is a high-yield topic because physical address calculation is often asked.

• Logical address is represented as segment:offset.
• Physical address = segment x 16 + offset.
• CS:IP points to instruction fetch address.
• DS usually points to data segment.
• SS:SP points to stack location.
• Segment registers allow 20-bit physical addresses using 16-bit register values.

Memory and I/O Interfacing

Interfacing means making sure the correct chip responds to the correct address and read/write signal.

• Address decoding selects memory or I/O chip for a given address range.
• Data bus carries actual data between processor and device.
• Control lines such as RD, WR, IO/M or M/IO indicate operation type.
• Tri-state buffers prevent multiple devices from driving bus simultaneously.
• Latch may be required to demultiplex address/data lines in processors with multiplexed buses.
• Peripheral chips such as 8255 PPI, 8253/8254 timer and 8259 interrupt controller are common interfacing concepts.

Interrupts and Stack in Microprocessors

Interrupt handling is where software and hardware meet.

• Interrupt request causes CPU to save return address and transfer control to interrupt service routine.
• Stack stores return addresses, register values and temporary data.
• Maskable interrupts can be enabled/disabled; non-maskable interrupts are for critical events.
• Vectored interrupts have predefined or supplied ISR address.
• ISR should preserve registers it modifies and return with proper return-from-interrupt instruction.

Engineering Mechanism

• Processor fetches instruction from memory using PC/IP.
• Instruction decoder identifies operation and operand addressing mode.
• Registers/memory provide operands to ALU or control unit.
• ALU executes arithmetic/logical operation and updates flags.
• Control signals perform memory or I/O read/write.
• Address decoder selects the correct memory/peripheral device.
• Interrupts and stack allow asynchronous service and subroutine return.

Diagrams / Models To Draw

• Draw 8085 block diagram with registers, ALU, timing/control, address/data bus.
• Draw 8086 segmentation: segment register, offset and physical address calculation.
• Draw memory interfacing with address decoder, memory chip, data bus and RD/WR lines.
• Draw I/O interfacing using 8255-style peripheral ports.
• Draw interrupt service sequence and stack return address.

Formulas, Tables and Algorithms

• 8085 addressable memory = 2^16 = 64 KB.
• 8086 physical address = segment x 10H + offset.
• 8086 addressable memory = 2^20 = 1 MB.
• Chip select range depends on number of decoded address lines.
• Stack grows downward in many Intel conventions; PUSH decrements stack pointer then stores data.

Worked Example

If CS = 2000H and IP = 0150H in 8086, physical instruction address = 2000H x 10H + 0150H = 20000H + 0150H = 20150H. This is the address from which the next instruction byte is fetched.

Subjective Answer Pattern

• Define microprocessor and explain 808x context.
• Describe architecture: ALU, registers, buses, control unit and flags.
• Compare 8085 and 8086.
• Explain addressing modes and instruction categories.
• Explain memory/I/O interfacing with address decoding and control signals.
• Add interrupt/stack behavior and one worked address example.

Common Engineering Mistakes

• Confusing data bus width with address bus width.
• Forgetting 8086 physical address calculation uses segment shifted left by 4 bits.
• Writing assembly instruction names without explaining operands and flags.
• Ignoring chip select/address decoding in interfacing answers.
• Saying interrupt is same as polling.
• Not preserving registers in ISR explanation.

MCQ Revision

• What is 8085 address bus width?
• How much memory can 8086 address?
• Which register pair is commonly used as memory pointer in 8085?
• How is 8086 physical address calculated?
• Which chip is programmable parallel interface?
• Which flags are affected by arithmetic?

Final Summary

• 808x study combines processor architecture, assembly and hardware interfacing.
• Registers, flags, buses and control signals explain instruction execution.
• 8086 segmentation is essential for address calculation.
• Interfacing requires address decoding, chip select and read/write timing.
• Interrupts and stack support asynchronous service and subroutine control.