Digital logic is the mathematical and circuit foundation of computer hardware. PSC Computer Engineer questions may ask Boolean simplification, universal gates, adder design, decoder/multiplexer operation and combinational circuit design from a truth table.

Engineering Definitions

Digital logic

Standard definition: The branch of electronics that represents and processes information using discrete binary values.

Exam meaning: 0 र 1 signal प्रयोग गरेर hardware decision र computation बनाउने आधार।

Logic gate

Standard definition: An electronic circuit that performs a Boolean operation on one or more binary inputs.

Exam meaning: AND, OR, NOT, NAND, NOR, XOR जस्ता Boolean operation गर्ने circuit।

Boolean algebra

Standard definition: An algebraic system for manipulating logical variables and operations.

Exam meaning: Binary variables र logic operations simplify गर्ने गणित।

Combinational circuit

Standard definition: A logic circuit whose output depends only on present input values.

Exam meaning: Memory नभएको, current input बाट मात्र output दिने circuit।

Karnaugh map

Standard definition: A graphical method for simplifying Boolean expressions by grouping adjacent minterms or maxterms.

Exam meaning: Truth table बाट Boolean expression simplify गर्ने visual method।

Concept Teaching

Digital circuit design starts from specification. Convert requirement into truth table, derive Boolean expression, simplify using algebra or K-map, then implement using gates. Combinational circuits do not store past state, so delay and hazards matter but memory does not.

Boolean Algebra Laws

Simplification becomes faster when common laws are automatic.

  • Identity: A + 0 = A, A . 1 = A.
  • Null: A + 1 = 1, A . 0 = 0.
  • Idempotent: A + A = A, A . A = A.
  • Complement: A + A bar = 1, A . A bar = 0.
  • De Morgan: (A . B) bar = A bar + B bar; (A + B) bar = A bar . B bar.
  • Absorption: A + AB = A; A(A+B) = A.

Logic Gates and Universal Gates

NAND and NOR are universal because any Boolean function can be built using only one of them.

Gate Operation High-yield point
AND Output 1 only when all inputs are 1 Product term
OR Output 1 if any input is 1 Sum term
NOT Inverts input Complement
XOR Output 1 for odd number of 1s Useful in adders/parity
NAND NOT of AND Universal gate
NOR NOT of OR Universal gate

Canonical Forms

Canonical expression uses all variables in every term and connects truth table to Boolean expression.

  • Sum of Products uses minterms where function output is 1.
  • Product of Sums uses maxterms where function output is 0.
  • Minterm corresponds to one row of truth table with output 1.
  • Maxterm corresponds to one row of truth table with output 0.
  • Canonical form is systematic but not necessarily minimal.

K-map Simplification

K-map grouping reduces gates and levels.

  • Adjacent cells differ by only one variable due to Gray-code ordering.
  • Group sizes must be powers of two: 1, 2, 4, 8 and so on.
  • Use largest possible groups to reduce literals.
  • Groups can wrap around edges.
  • Do not-care conditions can be used as 0 or 1 to simplify expression.
  • Prime implicants and essential prime implicants guide minimal cover.

Adder, Subtractor and Comparator

Arithmetic circuits are common design questions.

  • Half adder adds A and B: Sum = A XOR B, Carry = AB.
  • Full adder adds A, B and Cin: Sum = A XOR B XOR Cin.
  • Ripple-carry adder chains full adders but carry delay accumulates.
  • Subtractor can be built using two’s complement addition.
  • Comparator checks equality or magnitude using XOR/XNOR and logic gates.

MUX, DEMUX, Encoder and Decoder

These are MSI building blocks used in datapath and control circuits.

Circuit Function Typical exam point
Multiplexer Selects one of many inputs to one output 2^n inputs need n select lines
Demultiplexer Routes one input to one of many outputs Opposite selection direction
Encoder Converts active input line to binary code Priority encoder handles multiple active inputs
Decoder Converts binary code to one active output n inputs produce up to 2^n outputs

Engineering Mechanism

  • Write truth table from required input-output behavior.
  • Identify minterms or maxterms.
  • Simplify Boolean expression using algebra or K-map.
  • Choose implementation gates such as AND-OR, NAND-only or NOR-only.
  • Draw circuit and verify all truth table rows.
  • Check propagation delay and possible hazards if timing matters.

Diagrams / Models To Draw

  • Draw basic gates with truth tables.
  • Draw NAND-only implementation of NOT, AND and OR.
  • Draw 3-variable or 4-variable K-map with groupings.
  • Draw half adder and full adder.
  • Draw 4-to-1 MUX and 3-to-8 decoder.

Formulas, Tables and Algorithms

  • Half adder: S = A XOR B, C = AB.
  • Full adder: S = A XOR B XOR Cin.
  • MUX inputs = 2^select lines.
  • Decoder outputs = 2^input lines.
  • De Morgan laws: (AB) bar = A bar + B bar; (A+B) bar = A bar B bar.
Concept Purpose Exam distinction
Boolean algebra Simplify logic expression Use laws correctly
K-map Visual minimization Group powers of two
NAND/NOR Universal implementation Can build any logic
Adder Binary arithmetic XOR is central in sum
MUX Data selector Select lines choose input
Decoder Binary-to-one-hot output Memory/address decoding use

Exam Point

  • For design questions, show truth table before final circuit.
  • Use K-map grouping rules and mention do-not-care use.
  • Remember NAND and NOR are universal gates.
  • MUX/decoder select-line formulas are frequent MCQs.
  • Differentiate combinational circuit from sequential circuit clearly.

Worked Example

For a half adder, inputs A and B produce sum 1 when inputs differ, so S = A XOR B. Carry is 1 only when both inputs are 1, so C = AB. This simple circuit becomes the base for a full adder by adding carry-in.

Subjective Answer Pattern

  • Define digital logic and combinational circuit.
  • Explain Boolean algebra and gate operations.
  • Show truth table and canonical form.
  • Simplify using K-map or laws.
  • Explain key combinational blocks: adder, MUX, decoder, encoder.
  • Conclude with implementation and delay/hazard awareness.

Common Engineering Mistakes

  • Grouping non-adjacent K-map cells.
  • Forgetting K-map groups must be powers of two.
  • Confusing encoder and decoder direction.
  • Saying MUX has n inputs for n select lines instead of 2^n.
  • Mixing combinational and sequential examples.

MCQ Revision

  • Which gates are universal?
  • What is half-adder sum expression?
  • How many select lines for 16-to-1 MUX?
  • How many outputs for 3-to-8 decoder?
  • What is De Morgan theorem?
  • What does a K-map simplify?

Final Summary

  • Digital logic uses Boolean algebra to build hardware from binary signals.
  • Combinational circuits depend only on current inputs.
  • K-map and Boolean laws reduce gate count.
  • Adders, MUX, decoders and encoders are core building blocks.
  • Universal gates allow NAND-only or NOR-only implementation.