4.2 Von Neumann, Harvard, RISC and CISC
Advanced engineering study guide on Von Neumann and Harvard architectures, stored-program concept, memory bottleneck, RISC, CISC, ISA design and performance tradeoffs.
4.3 Data Representation, Arithmetic, Bus and Instruction Cycle
Advanced engineering study guide on number systems, signed representation, complements, overflow, ALU arithmetic, bus organization and instruction cycle.
4.4 Addressing Modes, I/O, Interrupt, DMA and Memory Systems
Advanced engineering study guide on addressing modes, effective address calculation, I/O techniques, interrupts, DMA, memory hierarchy, cache and virtual memory.
4.5 808x Intel Microprocessor Programming and Interfacing
Advanced engineering study guide on 8085/8086 family concepts, registers, addressing, instruction execution, assembly programming and peripheral interfacing.
4.6 Digital Number Systems, Logic Gates and Combinational Circuits
Advanced engineering guide to digital number systems, Boolean algebra, logic gates, minimization, adders, multiplexers, decoders and combinational circuit design.
4.7 Sequential Logic, Counters, Registers and IC Families
Advanced study guide on sequential logic blocks, counters, shift registers, timing, race hazards and digital IC families.
4.8 Electrical Circuits: AC, Transformers, Filters and Transients
Advanced study guide on DC/AC circuit laws, phasors, impedance, resonance, transformers, filters and transient response.
4.9 Semiconductor Diodes, Transistors, Amplifiers and Op-Amp
Advanced engineering guide to semiconductor basics, PN junction diode, rectifiers, BJT/FET, amplifiers, feedback and operational amplifier circuits.
4.10 Electronic Communication: Modulation, Error Control, SNR and BER
Advanced engineering guide to analog/digital communication, modulation, multiplexing, noise, SNR, BER, channel capacity and error control coding.
4.1 Sequential Circuits, State Table and Architecture
Advanced engineering study guide on sequential circuits, latches, flip-flops, state tables, state diagrams, timing, FSM design and architecture links.